System Circuit Analysis And Design An Integrated Operation Amplifier Report Samples

System Circuit Analysis and Design an Integrated Operation Amplifier

Introduction
The amazing device called operational amplifier (op-amp) is a solid state IC which has the abilities to use external feedback to control its operations. As one of the most versatile device in the state-of-art solid state electronics technology till date, op-amp has been used with several different and remarkable functions. Apart from its use as a high gain amplifier, it has been typically used to device analog computers, various amplification requirements where high gain is required, cmos, short circuit protection, low input current frequency compensation and a myriad of different functionalities.
Equally interesting has been the evolution of the op-amps. From the first solid-state monolithic op-amp, which came to public, was in 1963. This op-amp was designed by Bob Widlar and manufactured by Fairchild semiconductors was named as ua702 and from this time, the evolution of op-amps have been dramatic. There have been different stages of evolution; in FETs development, op-amps were able to accept very low input current. Overall, as of today, the op-amps are known to have following features:
internal frequency compensation
short circuit protection
offset voltage null capacity
excellent temperature stability
high input voltage range
no latch-up
In the following section, the objectives would be to demonstrate the basic understanding of analogue ICs, followed by demonstrating the abilities to prove that we can accurately simulate an analogue IC and finally an attempt will be made to design a good IC. Overall, I have tried to make best possible attempt to present this ‘engineering report’ in a professional manner.
1. Analysis – Given a basic analogue IC with 4 transistors.
The scheme of the integrated operational amplifier modifies to the depicted on Fig. 1. The basic building blocks of the circuit are as described below:

Base resistors to limit base current to transistors.

Current sense resistor to switch on transistor
Transistor to supply the load current and the current limiting transistor
There are probes to measure the voltage, current and frequency
Oscilloscope for signal analysis
An approximate DC analysis is performed with β >> 1, so that the base current of every transistor can be ignored. The attempt is made to analyze the circuit diagram 1 as given. The calculations and descriptions are given below for evaluating the following parameters:
i. The DC collector currents in the circuit
ii. The DC collector voltage in the circuit
iii. The Quiescent Power Dissipation in the circuit (PD)
iv. Total voltage Gain
v. ac characteristics of the circuit --- total voltage gain, IO Impedance, CMRR, Max Output voltage swing

Assumptions:

β = 120(NPN), 60 (PNP)
Early Voltage = 100 (NPN), 75 (PNP)

Op-amp has very high input impedance (MOhms)& Low output impedance (10 – 100 Ohms),

very high voltage gain (> 10000 = 80 dB) and very high CMRR (> 80dB)
We assume that this is a simple circuit, as we assume that the op-amp is an ideal one, although practically it is difficult to find an ideal op-amp

The DC collector voltage and currents in the circuit are as given below.

Q1 is a NPN –transistor with a common collector, the input signal is applied to the base, and the output signal is the emitter. The input resistance is rім= R1β+1≈0.67 mOhm.The voltage gain AV ~ 1.Therefore, the voltage at A is to be found. The Q1 resistor (collector and emitter), taking into account the voltage and ß as 10.6 kOhm, and resistance Q2 = 6.8 kOhm. The resistance of the electric circuit link Q2 – Q2 – R2:
RQ12= 10.6 (6.8+4.7)10.6+6.8+4.7= 121.922.1≈5.5 kOhm
Then, the potential in А: -10+R1 ∙ 20RQ12 ≈ -0.6 V

This voltage is used for amplitude periodic signal V1.

Q2 is a NPN-transistor with a common base, the input signal is the emitter signal, and the output signal is the collector signal.
The switching at β=120 and Ic≈Ie (the collector current is equal to emmiter), it is possible to find a potential in B:
VB = 10- R2∙ 11.66.8+4.7≈5.3 V

The output signal Q2 is a input signal Q3.

Thus, the signal in B is to be found. The amplification factor by voltage for the scheme with a common base:
Av~gmRc=IcVTR2=12.6V25 mV∙11.5kOhm∙4.7kOhm≈169.2

Thus, the signal amplitude for B is about 170 Vin.

The potential in B: 5.2R + 170 Vin.
Q3 is a PNP-transistor connected to the circuit with the common emmiter, the input signal is the base signal, and the output signal is the collector signal.
Following the same procedure, it is found that the constant potential in C is equal to 1.5 V, and the amplification factor is:
Av~-3.11=3.1, the “-“ sign shows that the signal is inverted.
Therefore, Vc ≈ 1.5V -524V1.
Q4 is a NPN-transistor connected to the circuit with the common collector, the input signal is the base signal, and the output signal is the collector signal.

Av~1,

while RQ4=0.9kOhm.
Therefore, Vo(const) ≈10+ 20∙ R5R5∙ RQ4≈0.5V.
Thus, VD= 0.5V - 524Vin.
If an input signal is Vin=10 mV , then Vout=5∙24 V
The outlet resistance Rout=R=1 kOhm

Voltage amplification is Av(total)≈524

CMRR (db-Common mode rejection ratio is given as follows:
CMRR = 20log10AdAcm
AD=0.520;
ACM=524;

CMRR≈86.4dB

\
The power supply (Vcc) in the range + 10 V - 10 V is used to supply energy to the circuit. Earth is applied for voltage sampling. The resistance elements R1 - R6 are used for voltage control, the transistors (Q1 and Q2 with the common base, Q3, Q4 with the common emitter for signal amplification.

For the direct current,

IQ=IK , IS=0.

The scheme of the integrated operational amplifier modifies to the depicted on Fig. 2

Figure 2. The modified scheme of the integrated operational amplifier (DC operation).
R1=4.7kOhm
R2=4.7kOhm
R3=2 kOhm
R4=3.1 kOhm
R5=1 kOhm
The scheme can be changed to the equivalent (Fig. 3).
Figure 3. The equivalent scheme.
On the scheme, R12=4.7+4.7=9.4 kOhm
R34=1+3.1=4.1 kOhm
I1=20VR12=2.1 mA
I2=20VR34=4.9 mA
I3=20VR5=20 mA

The potential in A is calculated:

VA=-10V+I1∙R1=0 V
VB=-10V+I2∙R4≈5.1 V
Therefore, the signal on oscillograph: V=10V , I=20mA.

Quiescent Power Dissipation is given as:

PDQ=Vcc∙I1+I2+I3≈0.54 W
Gain=10logVout2RoutVin2Rin=4.3 dB.

The results are summarized as follows:

A
2. Analysis - Simulation
The Multisim simulated results differ from the data by the optimal operational feeder. This is due to the necessity of adding the additional elements to the scheme (current mirrors, cascade differential amplifiers, Darlington pairs).

The circuits are constructed using the multisim software as shown below:

The results are obtained by running the simulation as shown in the below figure:
The oscilloscope analysis is shown below:
The comparison of Multisim results and the calculations are presented in Table 1.
Apparently, the results are approximate. The discrepancies might be explained by errors at determination of collector-emitter channel resistance of the transistor of early voltage, as well as neglecting the base currents.
3. Design

The designed scheme and its characteristics are presented on Figure 4.

Basically some improvements have been made to the basic diagram 1 as given. The design is made using the multisim software and the simulation is run. The results are captured and presented in the below section.
Figure 4. The equivalent scheme.
The overall design is attempted to be improved by introducing a capacitor and increasing the value of resistance. The introduction of the capacitor is based on the rationale that it will lower the frequency and increase the overall voltage gain and improved CMRR. (Analog Integrated Circuits, nd)

The new readings are as follows:

Conclusion
The given circuit was analyzed using manual calculations and then the design was put in NI multisim software. The design of the circuit was re-evaluated using the simulation feature of the software. The observed reading were recorded and it was found that there were certain discrepancies. One major reason for the deviation could be that we assumed the parameters for an ideal op-amp or the conditions were idealistic. However, such conditions are usually not available in the practical sense. Other factor which resulted in the discrepancies were explained by errors at determination of collector-emitter channel resistance of the transistor of early voltage, as well as neglecting the base currents. Finally some improvements were suggested from the given circuit. A small research was done to get the recommendations and best practices for improving the analog circuits. Two such features were added for the overall improvements of the design.

References.

Analog Integrated Circuits (nd). Retrived from http://highered.mheducation.com/sites/dl/free/0070601623/337358/jae20990_ch16.pdf
Integrated Design and Test Platform with NI Multisim (nd) Retrieved from http://www.ni.com/pdf/products/us/cat_nimultisim.pdf